1. Field of the Invention
The present invention relates to a microcomputer system, and more particularly to apparatus and method for extending memory addressing.
2. Description of Related Art
In microcomputer systems, CPUs (Central Processing Units), buses and memories are kernel parts. Buses include a data bus and an address bus, the former is used to transmit data among devices, the latter is used to transmit addresses of the data. The direct addressing space of the CPU depends on the width of the address bus. For example, the direct address space of a 20-bit address bus is 1 MB, while the direct address space of a 24-bit address bus can reach 16 MB.
With the development of technology, the processing power of a CPU improves dramatically. Meanwhile, the capacity of the memory is becoming larger and larger. However, because of the limits in the width of the address bus, the addressing space of the CPU is limited. Hence, techniques for extending addressing space are desired.
One conventional approach to extend the addressing space is shown in FIG. 1. The apparatus 100 includes a Direct Addressing Memory (DAM) 110, a mapping unit 150 and N extended memories 140, where N is a finite integer. Each data cell of the DAM 110 can be directly addressed according to address signal transmitted over an address bus 120. It is assumed that the width of the address bus 120 is designated as Wa and the width of a data bus is designated as Wd, the maximum amount k of the data cells in the DAM 110 is equal to 2Wa, the size of each data cell is equal to the width Wd of the data bus 130.
After acquiring the address signal from the address bus 120, the DAM 110 finds corresponding data cell thereof according to the address signal, subsequently, writing data in the data bus 130 into the data cell or providing data from the data cell and exporting them to data bus 130. The mapping unit 150 finds data cells of corresponding extended memories 140 according to data information stored in the DAM 110 and establishes a mapping relationship between data cells of the extended memories 140 and the corresponding data cells of the DAM 110. Thus, the CPU can access the data cells of the extended memories 140 by means of accessing the data cells of the DAM 110.
Referring to FIG. 2, the data cells of the DAM 110 is mapped onto the data cells of the extended memories 140. Every two neighboring data cells of the DAM 110 work as one group which corresponds to one of the extended memories 140. The first data cell of one group is used to store the address of a corresponding extended memory (i.e., one of the N memories 140). The second one of the one group is mapped onto one data cell of the corresponding extended memory. Specifically, the data cells 1 and 2 of the DAM work as one group which corresponds to the extended memory 1, where the data cell 1 is used to store the address of the extended memory 1, the data cell 2 is used as the mapping of one data cell of the extended memory 1. Analogically, the data cell 2N−1 and the data cell 2N work as one group which corresponds to the extended memory N. The data cell 2N−1 is used to store the address of the extended memory N. The data Cell 2N is used as the mapping of one data cell of the extended memory N.
The operation for extending addressing space can be described in conjunction with FIG. 2. When reading or writing operation is needed for a data cell s of an extended memory m, the CPU writes s into the data cell 2m−1 of the DAM. Because the extended memory m corresponds to the data cell 2m−1, the mapping unit 150 of FIG. 1 knows that the accessing operation is for the extended memory m. According to the value s in the data cell 2m−1, the mapping unit 150 finds the sth data cell of the extended memory m. Subsequently, the data cell 2m of the DAM is mapped onto the data cell s of the extended memory m. Finally, the CPU can achieve the indirect access operation to the data cell s of the extended memory m by means of directly reading or writing the data cell 2m of the DAM.
When the width of the address bus is Wa and the width of the data bus Wd, the maximum amount n of the extended memories which can be supported by extending addressing space to 2Wa−1, the maximum amount a of the data cells in each extended memory is equal to 2Wd. Therefore, the maximum extended addressing space is 2Wa+Wd−1.
It can be seen that the above extending approach must write the address of the data cell of the extended memory into the DAM every time before reading or writing operation to the data cell of the extended memory can happen. Only when the mapping relationship between the data cells is found, the reading and writing operation can be performed. The approach described above has to be repeated in each writing or reading operation to the data cell, thus seriously decreasing the processing speed of the system. Meanwhile, nearly a half of the DAM's space is used as the mapping of the data cell of the extended memory and another half is used for addressing, which results in smaller total extending addressing space.
Thus there is a need for techniques for extending addressing space with more accessed efficiency.